A magnetic recording read channel converts an analog read signal into an estimate of the user data recorded on a magnetic medium. Read heads and magnetic media introduce noise and other distortions into the read signal. As the information densities in magnetic recording increase, the intersymbol interference (ISI) becomes more severe as well, (i.e., the channel impulse response becomes longer). In a read channel chip, a Viterbi detector is often employed to detect the read data bits in the presence of intersymbol interference and noise.
Generally, Viterbi detectors employ maximum-likelihood decoding of convolutional codes to determine the shortest path through a code trellis. Viterbi detectors use the trellis structure and determine the maximum-likelihood estimate of the transmitted sequence. A survivor path is identified that is the most likely path having the largest accumulated metric through the trellis. The metric of all paths entering each state are compared and the survivor with the largest accumulated metric is maintained at each state.
A conventional Viterbi decoder 100, shown in FIG. 1, typically comprises a branch metric unit (BMU) 110, an add/compare/select unit (ACSU) 120, a survivor path memory unit (SPM) 130 and a decision feedback unit (DFU) 140. For a detailed discussion of conventional Viterbi decoders, see, for example, Borivoje Nikolic et al., “Read/Write Channel Implementation,” in Coding and Signal Processing for Magnetic Recording Systems, CRC Press, (2005, Bane Vasic and Erozan M. Kuratas editors), incorporated by reference herein.
Generally, as shown in FIG. 1, the decision-feedback unit 140 computes separate ISI estimates for each trellis state, the branch metric unit 110 computes branch metrics for all transitions, the add-compare-select unit 120 determines the best survivor path into each state, and the survivor path memory 130 stores the survivor paths.
Typically, a survivor path memory unit implements a register-exchange or trace-back architecture to generate the survivor symbols for each state. In a register-exchange survivor memory implementation, survivor symbols for each state are stored and updated at each detection step. In a trace-back implementation, ACS decisions are stored as pointers in a memory, and the detected symbols are obtained by tracing back the pointers that correspond to a survivor path.
The trace-back architecture does not require the updating of all survivor symbols at each detection step. Thus, the trace-back architecture is associated with less power consumption than the register-exchange architecture. The trace-back architecture, however, is associated with larger detection latency and therefore is generally not suitable for most Viterbi detection applications. The register exchange algorithm exhibits higher dynamic power consumption than the trace-back algorithm, because the register exchange algorithm requires one flip flop for each memory bit, and the whole memory contents is updated in each clock cycle of the register exchange algorithm, resulting in higher switching activity. The trace-back, on the other hand, only updates N memory bits in each clock cycle for an N-state radix-2 trellis.
A need therefore exists for an improved register exchange algorithm that features lower switching activity and power consumption.